1. Field of the Invention
The present invention relates to a process for forming a self-aligned low resistance path to a buried layer in a semiconductor device. The invention may also be applied to the formation of a self-aligned guard ring structure in the semiconductor device.
2. Description of the Prior Art
U.S. Pat. No. 4,261,095 Dreves et al discloses a process for producing a guard ring in a semiconductor device by creating an area under an undercut nitride layer (silicon dioxide being removed) overlying a semiconductor body to expose a contact area around the surface of the body and depositing a barrier material in the opening so that a small space is left around the outer edge of the deposited material and the recessed wall of the underlying silicon dioxide to permit diffusion of a narrow ring around the covered area. This process is more complex than that of the present invention, albeit it is self-aligned.
IBM Technical Disclosure Bulletin, Vol. 26, #9, February 1984, pp. 4498-4499, Chang et al teaches that an overetched oxide hole under a nitride layer can be used to form a polysilicon diffusion source for a guard ring on a semiconductor device.
IBM Technical Disclosure Bulletin, Vol. 21, #7, December 1978, p. 2752, Anantha et al teaches that a guard ring can be created by out-diffusion of boron during deposition of a polysilicon layer.
U.S. Pat. Nos. 4,135,955 Gasner et al; 4,223,334 Gasner et al and 4,468,852 Cerofolini teach various processes for making self-aligned guard rings in CMOS devices.